GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation

Process variations and device aging impose profound challenges for circuit designers. Without a precise understanding of the impact on delay paths, guardbands, which keep timing violations at bay, cannot be correctly estimated. This problem is exacerbated advanced technology nodes, where transistor dimensions reach atomic levels established margins are severely constrained. Hence, traditional worst-case analysis becomes impractical, resulting in intolerable performance overheads. Contrarily, process-variation/aging-aware static (STA) equips designers with accurate statistical distributions. Timing guardbands that small, yet sufficient, can then effectively However, such costly as it requires intensive Monte-Carlo simulations. Further, necessitates access to confidential physics-based models generate standard-cell libraries required STA. In this work, we employ graph neural networks (GNNs) accurately estimate process any path within circuit. Our proposed GNN4REL framework empowers perform rapid reliability estimations without accessing models, libraries, or even STA; these components all incorporated into GNN model via training by foundry. Specifically, trained FinFET calibrated against industrial 14-nm measurement data. Through our extensive experiments EPFL ITC-99 benchmarks, well RISC-V processors, successfully degradations paths—notably seconds—with mean absolute error down 0.01 percentage points.